Altera and Riverlane Partner on QEC Interfaces for Agilex FPGAs Following Post-Quantum Security Rollout

FPGA provider Altera (an Intel company) and quantum error correction (QEC) specialist Riverlane have announced a partnership to optimize real-time QEC data movement and low-latency control logic across Altera’s Agilex® FPGA portfolio. Under the agreement, Riverlane joined the Altera Solutions Acceleration Partner (ASAP) Program and validated its open-source QEC Interface (QECi) protocol on Altera Agilex 7 devices, establishing a standardized data-interchange framework between quantum control electronics and physical QEC decoders.

The technical integration addresses the microsecond latency constraints of fault-tolerant quantum computing by leveraging Agilex 7 F-Tile transceivers to route syndrome data between control stacks and decoder chips with deterministic timing. By publishing the open-source QECi reference design on GitHub, the partners provide QPU developers with a hardware-validated starting point for multi-qubit parallel processing and high-bandwidth readout across superconducting, trapped-ion, and silicon spin-qubit platforms. The collaboration also encompasses high-throughput Agilex 9 Direct RF FPGAs, which integrate direct digital-to-analog and analog-to-digital data converters operating up to 64 Gsps across a 36 GHz RF range.

The QEC collaboration follows Altera's September 8 announcement introducing native Post-Quantum Cryptography (PQC) support across its entry-level Agilex 3 and mid-range Agilex 5 FPGAs and SoCs. Built into the hardware via an updated Secure Device Manager (SDM) and supported by the Quartus® Prime Pro Edition 26.1.1 design software, the PQC-enabled architecture protects long-life defense, industrial, and edge infrastructure against harvest-now-decrypt-later attacks using quantum-resistant secure boot, bitstream encryption, key management, anti-tamper mechanisms, and platform attestation.

Together, the dual releases establish Altera's broader two-pronged quantum strategy: protecting classical hardware infrastructure against future quantum decryption via PQC-enabled Agilex 3/5 silicon while providing low-latency, deterministic control fabric for utility-scale QPU control via Agilex 7/9 FPGAs alongside Riverlane's Deltaflow QEC stack.

Review the QEC partnership press release via Altera here, read the post-quantum security announcement on Altera PQC Security here, access the open-source hardware integration code on GitHub here, and examine our previous analysis of Riverlane's Series C Funding and Deltaflow QEC Roadmap here.

September 10, 2026