BlueQubit Benchmarks Quantum Computational Advantage in Random-Circuit Sampling on IBM Nighthawk r2 Hardware

Researchers from BlueQubit, in collaboration with the Ecole Polytechnique Fédérale de Lausanne (EPFL) and the XPRIZE Foundation, have reported a demonstration of quantum computational advantage via random-circuit sampling (RCS) on commercial superconducting hardware. In a preprint titled Quantum computational advantage in random-circuit sampling on IBM superconducting quantum computers, the team executed forward RCS on IBM Quantum's 120-qubit ibm_phoenix processor, which uses the square-lattice Nighthawk r2 architecture. Operating over 61 active qubits using native controlled-Z (CZ) gates, the circuits were submitted through standard Qiskit Runtime cloud queues without bespoke hardware calibration, yielding an output ensemble that would require over a century to sample classically under baseline rejection-sampling assumptions.

Circuit Construction, Dual Fidelity Verification, and Contraction Complexity

The experiment deployed a four-color brickwork schedule (cycling through matchings A, B, C, and D) across 102 active couplers, averaging 25.5 native CZ operations per cycle. Rather than relying solely on extrapolation, the team established fidelity across depths ranging from 4 to 40 cycles using two independent methodologies: mirror benchmarking with randomized compiling and multi-partition cross-entropy benchmarking (XEB) across three and four balanced patches. At the anchor depth of 36 cycles (incorporating 918 CZ gates), where tensor-network contraction costs saturate at full system size with a width of w = 64, the experimental fidelity reached F_XEB ≈ 2.3 × 10⁻³. While the ibm_phoenix processor collected 10⁶ samples in 19 seconds of active quantum processing unit (QPU) time, reproducing that ensemble via tensor-network rejection sampling on the Oak Ridge National Laboratory Frontier supercomputer would require an estimated 1.2 × 10²⁷ machine floating-point operations (FLOPs)—amounting to roughly 110 years of exascale compute.

Classical Hardness Limits, Spoofing Margins, and Commercial Reproducibility

The study highlights architectural improvements between IBM processor generations: the per-cycle fidelity on the square-lattice Nighthawk r2 reached 0.872, compared to 0.836 on the first-generation Nighthawk r1 (ibm_miami), compounding to more than an order-of-magnitude fidelity gain at deep cycle depths. To evaluate vulnerabilities common to linear XEB metrics, the authors tested classical "severing attacks"—where cross-boundary couplers are deleted to simulate decoupled sub-circuits classically. At 36 cycles, all severing-attack modes scored below 2.2 × 10⁻⁴, falling at least an order of magnitude short of the experimental target score and confirming that the benchmark operates on the classically hard side of the noise-induced phase transition. However, the classical runtime estimate serves as an algorithmic baseline assuming exact single-amplitude contractions with unbounded memory; future classical developments in batched tensor slicing, matrix-product state approximations, or GPU-accelerated multi-amplitude reuse could lower classical runtimes, as observed in historical benchmarks against Google Quantum AI's Sycamore and USTC's Zuchongzhi processors.

Technical details and experimental validation data are published on arXiv, with open-source circuits, execution scripts, and the full 10⁶-sample dataset hosted on GitHub.

October 28, 2026