C12 Adopts QC Design’s Plaquette to Develop Fault-Tolerant Architectures

C12 has announced a partnership with QC Design to integrate the Plaquette design-automation platform into its development roadmap for fault-tolerant quantum computing. Plaquette will enable C12 to simulate and optimize its unique carbon nanotube (CNT) spin-qubit architecture under realistic noise models, simulating over 20 distinct hardware imperfections. This collaboration is specifically aimed at benchmarking Quantum Error-Correcting (QEC) codes, including high-rate Quantum Low-Density Parity-Check (QLDPC) codes, to identify the most efficient error-correction strategies for C12's scalable processors.

The C12 architecture utilizes isotopically purified carbon-12 nanotubes suspended above silicon chips to host spin qubits. This method maximally isolates the qubits from environmental noise, resulting in coherence times two orders of magnitude greater than traditional carbon-based circuits. By incorporating Plaquette, C12's theory teams can quantitatively evaluate how the physical parameters of these nanotubes impact logical qubit performance. The high-connectivity nature of C12's interconnect architecture is considered particularly compatible with the advanced QLDPC codes currently being analyzed within the software.

Based in Paris, C12 has raised over €25 million in funding to advance its materials-science-rooted approach to universal quantum computing. QC Design, headquartered in Ulm, Germany, provides the Plaquette platform as a cost-effective alternative to in-house design software, offering libraries of specialized codes and decoders. This partnership represents a transition for C12 from foundational physics experiments to the rigorous engineering phase required to demonstrate practical logical qubits on a scalable, fault-tolerant system.

For further details on the Plaquette simulation platform and the carbon nanotube roadmap, consult the official announcement here.

March 16, 2026