HRL Laboratories Demonstrates Self-Running Silicon QPU in Nature Benchmark

In a study published today in Nature, hardware developer HRL Laboratories—jointly owned by Boeing and General Motors—demonstrated an 18-qubit silicon spin quantum processing unit (QPU) that operates autonomously without real-time direction from room-temperature electronics. The integrated architecture replaces traditional racks of external control instruments with a custom cryogenic CMOS control chip operating at 4 K inside the cryostat. The system executed quantum error detection and repetition codes with zero room-temperature latency, addressing a critical scaling bottleneck in physical wiring and thermal management.

The unit integrates a 54-quantum-dot array (configurable for up to 18 exchange-only qubits) fabricated on 200mm isotopically enriched silicon-germanium wafers. To overcome the thermal bridge between control logic and sub-Kelvin qubits, HRL engineered a high-density, 296-channel superconducting niobium-on-polyimide ribbon cable. Operating at 4 K while drawing under 3.5 Watts, the 70-million-transistor 130nm RF-CMOS controller routes all 150 time-varying control waveforms to the mixing chamber with less than 10 microwatts of thermal load, maintaining qubit electron temperatures at 150 millikelvin.

System benchmarks showed an order-of-magnitude error reduction compared to prior exchange-only silicon spin demonstrations. The QPU achieved average single-qubit gate errors of 1.7×10⁻⁴ and CNOT entangling gate errors of 3.5×10⁻³, with lowest reproducible two-qubit errors reaching 9×10⁻⁴. Device charge noise dropped tenfold over previous gate electrode designs, enabling fast sub-microsecond gate execution while reducing absolute gate error contributions from charge noise down to 0.02%.

To validate fault-tolerant functionality, HRL executed autonomous syndrome extraction routines across distance-3 and distance-5 repetition codes, incorporating real-time leakage-reduction units (LRUs) to prevent state leakage out of the computational subspace. The distance-5 code achieved an error-suppression scaling factor of Λ_5/3 = 4.7. The team also executed a $[[4,2,2]]$ quantum error-detection code across six physical qubits, where post-selection on error-detecting syndrome measurements sustained two-logical-qubit state fidelity at 95% across three consecutive syndrome extraction rounds.

By demonstrating that silicon spin QPUs, control logic, and high-density interconnects can be manufactured on standard commercial semiconductor lines and operated inside a single commercial cryostat, HRL has established a manufacturing blueprint for full-scale quantum processors. The breakthrough comes as IBM moves to finalize its definitive agreement to acquire HRL Laboratories, positioning this cryogenic CMOS and silicon spin IP to complement IBM's fault-tolerant quantum hardware roadmap.

Review the official study in Nature here, watch the technical architecture video here, and inspect the corporate release here.

July 29, 2026