Quantinuum Demonstrates Helix Quantum Error Correction Architecture on Helios Hardware

Trapped-ion quantum computing developer Quantinuum (NASDAQ: QNT) has announced the experimental validation of its Helix quantum error correction (QEC) architecture on its 98-qubit commercial processor, Helios. Detailed in a published research paper, the demonstration validated a complete fault-tolerant stack—spanning protected logical memory, high-speed logical Clifford computation, and inter-code logical entanglement—outperforming unencoded physical baselines across all benchmarked operations without relying on postselection.

The Helix architecture is built on the [[20, 2, 6]] C4-Helix code, a concatenated symplectic double code that pairs a [[10, 2, 3]] twisted toric code with a [[4, 2, 2]] block code. By utilizing the reconfigurable 2D shuttling capabilities of Quantinuum’s Quantum Charge-Coupled Device (QCCD) architecture, the code implements non-planar torus topologies to deliver a 3.5× reduction in spatial qubit overhead compared to traditional rotated surface codes of equivalent distance. In a 20-round memory benchmark under active syndrome extraction and hardware-level leakage repumping, Helix achieved a world-record logical memory error rate of 4.6 × 10^-5 per logical qubit per cycle (9.3 × 10^-5 block logical error per round), which further dropped to 1.9 × 10^-5 with 0.5% forced-gap decoder postselection.

To eliminate serial gate execution and expensive lattice surgery, Helix executes the complete two-qubit logical Clifford group using depth-1 transversal gates and permutation-based automorphisms driven directly by software-level qubit relabeling and ion transport. Two-qubit randomized benchmarking (TQRB) across the code's two logical qubits yielded a logical Clifford error rate of 2.8 × 10^-4 per gate—a 4.28× fidelity improvement over unencoded physical two-qubit Clifford gates (1.2 × 10^-3) on the same hardware. Performance was augmented by real-time Adaptive Syndrome Extraction (ASE), which pruned physical two-qubit gate counts by 33% and shortened per-shot execution times by 23%.

Addressing universal quantum computation, Quantinuum demonstrated a heterogeneous code architecture that couples memory and Clifford operations in Helix with dedicated magic-state distillation codes. Using a depth-2 chain-map CNOT interface, the team prepared a three-logical-qubit GHZ state spanning one [[25, 1, 5]] rotated surface code block and two C4-Helix logical qubits, achieving an entangling fidelity lower bound of 99.925% (upper bound of 99.975%), outperforming the physical three-qubit GHZ baseline (99.537%). The result validates the physical-layer primitives required to inject non-Clifford resource states into Helix memory, providing a blueprint for the company's upcoming fault-tolerant Apollo hardware generation.

Circuit-level simulations indicate that anticipated hardware-level gate fidelity enhancements on upcoming hardware generations will drive this exact [[20, 2, 6]] code into the 10^-6 to 10^-8 logical error rate regime without increasing code distance or adding physical qubit overhead. Furthermore, higher-distance concatenated variants—including the [[60, 2, 12]] Carbon-Helix and [[100, 2, 18]] Double-Helix codes—provide direct architectural scaling pathways to maintain low-overhead transversal and automorphism-based Clifford computation as system sizes expand.

Review the official announcement blog here, access the full technical research paper on arXiv PDF here, read our earlier coverage of Quantinuum's CHIPS Act agreement here, and examine our previous analysis of Fault-Tolerant Trapped-Ion Blueprints here.

September 9, 2026