Quantinuum Implements High-Rate Iceberg Codes on Helios Processor

Quantinuum implemented high-rate quantum error correcting (QEC) codes on the 98-qubit Helios trapped-ion processor, utilizing the [[k+2, k, 2]] iceberg quantum error detecting (QED) and [[(k₂+2)(k₁+2), k₂k₁, 4]] two-level concatenated iceberg QEC codes. This implementation yielded 94 error-detected logical qubits and 48 error-corrected logical qubits from the 98 physical qubits available on the system. The high-rate encoding achieved a physical-to-logical qubit ratio near 2:1 for error correction and approximately 1:1 for error detection, enabled by the all-to-all connectivity inherent in the trapped-ion architecture.

The logical qubits demonstrated "beyond break-even" performance, exhibiting error rates 10 to 100 times lower than their physical counterparts across multiple benchmarks. To achieve these fidelities, the architecture employed code concatenation, a nesting technique where error-detecting iceberg codes are layered to create a code distance of 4 capable of autonomous error correction. Benchmarking of these logical components included state preparation and measurement (SPAM), logical gate operations, and cycle benchmarking, confirming that error suppression remained effective during complex circuit execution.

The functionality of the encoded system was verified through a partially-fault-tolerant (pFT) quantum simulation of the three-dimensional XY model of quantum magnetism using 64 error-detected logical qubits. Additionally, the team generated a 94-logical qubit Greenberger-Horne-Zeilinger (GHZ) state, achieving a state fidelity of 94.9%. These applications utilized the processor's capability to execute non-local interactions to map 3D material lattice geometries onto the physical qubit layout, validating the system's capacity for large-scale logical computation.

For full technical details and the scientific paper, consult the official Quantinuum announcement here and the arXiv paper here.

March 14, 2026