QuiX Quantum Launches 'Dedalo' Photonic Architecture to Address Photon Loss via Single-Basis Logical Qubits

Photonic hardware engineer QuiX Quantum has published a comprehensive hardware blueprint detailing Dedalo, a new full-stack system architecture designed to achieve universal, fault-tolerant photonic quantum computing. The roadmap targets the foundational physical bottleneck of optical quantum configurations—photon loss—by transitioning from raw probabilistic physical states to error-corrected logical qubits managed natively at room temperature.

By utilizing Complementary Metal-Oxide-Semiconductor (CMOS)-compatible silicon nitride (Si₃​N₄​) photonic integrated circuits (PICs) alongside standard telecommunications fibers, the system architecture establishes a modular, plug-and-play coprocessing footprint engineered for direct installation into standard 19-inch high-performance computing (HPC) server racks.

┌──► Pseudo-Deterministic Photon Generator (SFWM micro-rings & FFCU switches) [ Dedalo Core ] ──┼──► Primitive State Generator (Photon distillation & small GHZ/Bell states) └──► Universal Quantum Processor (Type-I/II fusion networks & loss-tolerant beds)

The Architecture of Error-Heralded Measurement-Based Quantum Computing

Unlike solid-state modalities that rely on localized, gate-based physical interactions inside complex sub-kelvin dilution refrigerators, the Dedalo architecture operates within a Measurement-Based Quantum Computing (MBQC) framework. In an optical network, photons cannot be trapped easily and traditional two-qubit logic gates are inherently probabilistic. MBQC resolves this by bypassing gate execution entirely; computations are driven exclusively by a predefined sequence of single-qubit measurements performed across a highly entangled, continuous resource state known as a graph state.

To protect fragile quantum information from inevitable attenuation or absorption errors as light travels through silicon tracks, Dedalo implements an [[n,k,d]] stabilizer code layout. This protocol redundantly groups multiple physical photons into unified logical qubits capable of sustaining a structural loss threshold of d−1 photons without corrupting the computational matrix.

Because the architecture employs a discrete variable dual-rail encoding scheme—where a single photon passes through an on-chip Mach-Zehnder Interferometer (MZI) pair mapping computational states—the exact space and time coordinates of a missing photon are instantly flag-heralded upon measurement, allowing background classical processors to intercept, isolate, and correct erasure channels before phase-flip cascading occurs.

[ Technological Modality Profiling ] Cryogenic Systems ──► Requires massive energy loading to sustain sub-kelvin transmon or spin lattices. Dedalo Photonics ──► Maximizes room-temperature tracking; uses compact ~4 K cryostats only for PNR readouts.

The Three-Tiered Photonic Manipulation and Pulse Routing Stack

The physical execution of the Dedalo platform is organized across three tightly synchronized, hardware-isolated modular subsystems:

1. Pseudo-Deterministic Photon Generator: Multiple heralded photon generation loops operate concurrently on-chip. Individual micro-ring resonators execute spontaneous four-wave mixing (SFWM) to generate signal and idler photon pairs. As the idler photon hits an integrated detector, a high-speed Feed-Forward Control Unit (FFCU) triggers an array of electro-optical switches, routing the corresponding signal photon into the computation layer synchronously.

2. Primitive State Generator: The incoming synchronous signal photons pass through an optical distillation filter to eliminate spatial variations and maximize particle indistinguishability. The refined photons enter localized state generation cells that probabilistically produce small entangled primitive states, such as 3-particle Greenberger-Horne-Zeilinger (3-GHZ) and Bell states, which are monitored by local heralding detectors.

3. Universal Quantum Processor: An active fusion network leverages automated switching matrices to grab the successfully generated primitive states, routing them through on-chip silicon nitride delay lines to execute Type-I and Type-II fusion operations. This physical merging generates the overarching loss-tolerant logical resource state. The FFCU then applies dynamic phase adjustments to the MZI elements, performing logical-basis measurements to resolve the targeted computational workload.

To optimize the hardware stack for future utility-scale deployments, QuiX Quantum is partnering with European semiconductor foundries to integrate heterogeneous electro-optic materials for faster switching networks, implement low-dispersion waveguides to boost SFWM efficiency, and develop optimized facet geometries to compress chip-to-fiber insertion coupling losses.

While the first-generation Dedalo platform is structurally limited to Clifford-group logical basis measurements, the company’s long-range roadmap introduces parallelized, offline magic-state distillation pipelines to inject non-Clifford states into the resource fabric, establishing a scalable, modular pathway to achieve full fault-tolerant universality across distributed data center networks.

The full physical routing schematics, loss-threshold metrics, and component-level optimization logs can be reviewed in the official QuiX Quantum system architecture white paper here, with high-level corporate deployment timelines and telecom infrastructure compatibility profiles hosted in the QuiX Quantum Press Room here.

June 30, 2026