University of Sydney Demonstrates Multi-Qubit Logical Entanglement and 170-Round Stability on IBM Square-Lattice Nighthawk r2 Processor
University of Sydney researchers have demonstrated significant advancements in quantum error correction on IBM Quantum's ibm_phoenix processor. …

Researchers from the University of Sydney have demonstrated multi-qubit fault-tolerant logic and sustained error suppression on IBM Quantum's cloud-deployed ibm_phoenix processor, a 120-qubit superconducting system based on the square-lattice Nighthawk r2 architecture. The experimental findings, reported in an arXiv preprint (arXiv:2610.32347) and highlighted by IBM Research, validate distance-3 and distance-5 rotated surface code memories, logical Bell-state preparation via lattice surgery, and state and gate teleportation across three logical qubits. The results mark the first major multi-qubit logical benchmark executed on the platform just 54 days following its fleet integration.
Dynamic Role Alternation and Multi-Round Stability Benchmarks
A primary bottleneck in multi-round superconducting quantum error correction (QEC) is population leakage into non-computational states (such as the |2⟩ transmon state). While ancilla qubits are reset following syndrome measurements, data qubits remain unmeasured during stabilizer cycles, allowing leakage errors to accumulate and saturate error-suppression scaling. To circumvent this degradation, the University of Sydney team implemented a dynamic "walking" syndrome circuit that alternates the physical roles of data and ancilla qubits on successive rounds. By swapping functional roles at each time step, every physical qubit across the active patch undergoes measurement and hardware reset every two rounds, clearing non-computational leakage states before they spread into uncorrectable correlated logical faults.
University of Sydney QEC Experimental Benchmarks on ibm_phoenix | ||
Operational Metric | Demonstrated Value | Fault-Tolerant System Significance |
Processor Architecture | ibm_phoenix (120-qubit Nighthawk r2) | Features square-lattice planar connectivity and fast hardware active reset. |
Memory Error per Round | < 1% (Distances d = 3 and d = 5) | Maintains logical memory suppression below fault-tolerant thresholds. |
Logical Bell-State Fidelity | > 93% State Fidelity | Entangles two planar logical qubits via patch merging and splitting in lattice surgery. |
Three-Logical-Qubit Teleportation | 78% to 93% Process Fidelity | Executes state and gate teleportation protocols across three distinct encoded patches. |
Long-Duration Stability | ∼ 2 × 10−7 Error Probability | Achieves sustained error suppression out to 170 rounds (8 failures in 50 million runs). |
Lattice Surgery and Architectural Scaling Realities
The demonstration advances the execution of fault-tolerant operations from static memory preservation to multi-patch transversal and measurement-based logic. While earlier generations of IBM processors relied on heavy-hex layouts that required auxiliary flag qubits or modified compass codes, the square-lattice topology of Nighthawk r2 provides the direct nearest-neighbor connectivity needed for standard rotated surface code syndrome extraction. However, scaling lattice surgery across multi-logical architectures toward deep quantum algorithms will require mitigating residual cross-talk on denser square lattices, preserving two-qubit gate fidelities during concurrent mid-circuit readouts, and sustaining sub-microsecond classical decoder response times to support real-time feed-forward branching.
The preprint is indexed on arXiv, with ecosystem context outlined in IBM Research's QEC Retrospective.
October 28, 2026
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